Sparsity-Aware Path Planning Accelerator
FPGA acceleration for autonomous path planning.
This project accelerates autonomous path planning by targeting the quadratic programming bottleneck with FPGA-based hardware/software co-optimization.
The design exploits sparsity, memory optimization, task-level parallelism, and operator-level pipelining. It improves speed and power efficiency over CPU and embedded baselines.
Links: ICCAD 2024, FPGA 2024 poster.
Journal extension: ACM TACO, 2025, “A Sparsity-Aware Autonomous Path Planning Accelerator with HW/SW Co-Design and Multi-Level Dataflow Optimization.”