experience
Research and industry experience, teaching, awards, activities, and education.
Research Experience
CoVA: Compiler for Versatile Architectures (Ph.D. Thesis)
Jun. 2023 – Present, CORSA Lab, UC Irvine
Sole developer of an MLIR-based compiler that maps NumPy programs to CPUs and GPUs: a custom MLIR dialect and 30 passes lowering to six CPU/GPU code-generation routes, analyses that keep buffers GPU-resident, deterministic GPU reductions, and a PyTorch path for persistent model executables. The project was initiated during the 2023 HPE internship.
HeteroTask: Distributed Heterogeneous Task Runtime
Jan. 2025 – Apr. 2026, CORSA Lab, UC Irvine
Sole developer of a DAG execution framework with task-variant profiling, memory-aware device and variant selection, communication-cost modeling, and buffer lifetime planning, plus a C++/MPI runtime that executes the planned placements across CPU/GPU nodes. Its scheduling concepts later informed CoVA.
PyAIE: A Python-based Programming Framework for Versal ACAP
Sep. 2022 – Jun. 2023, CORSA Lab, UC Irvine
Led the design and implementation of a Python-based framework that generates AI Engine kernels, programmable-logic and host code, and configuration scripts for AMD Versal ACAP.
Industry Experience
Hewlett Packard Enterprise - Research Associate Intern
Jun. 2024 – Sep. 2024, Hewlett Packard Labs, Milpitas, CA · HeteroBench
Lead developer of HeteroBench, a benchmark suite of 11 multi-kernel applications with Python, OpenMP, CUDA, and HLS implementations for CPUs, GPUs, and FPGAs. Built a JSON-configured Python driver with Jinja-generated Makefiles for backend-specific builds, benchmark execution, profiler integration, and experiment logging. The work received the ICPE 2025 Best Paper Award - Artifact Track.
Hewlett Packard Enterprise - Research Associate Intern
Jun. 2023 – Sep. 2023, Hewlett Packard Labs, Milpitas, CA · CoVA
Built CoVA’s initial compilation framework: a custom MLIR dialect separating program semantics from target-specific lowering, MLIR-to-LLVM lowering, Python bindings, and compiler analysis and transformation passes.
IMBED LLC - Development Engineer Trainee
Sep. 2021 – Jan. 2022
Designed components for a real-time JPEG2000 player for digital cinema applications, with emphasis on FPGA implementation of the MQ entropy decoder.
Teaching
- Teaching Assistant, EECS 112L Organization of Digital Computers Laboratory, Fall 2026.
- Teaching Assistant, EECS 112 Organization of Digital Computers, Fall 2023.
Honors
- Best Paper Award - Artifact Track, ICPE 2025.
- Nominee, EECS Graduate Student of the Year Award, UC Irvine, 2024.
- Second-class Scholarship for Outstanding Students, Northwestern Polytechnical University, 2017 and 2018.
- Second Prize, 19th Undergraduate Mathematical Contest in Modelling, Northwestern Polytechnical University, 2018.
Activities
- Invited session chair and speaker, “Benchmarking in the Data Center: Expanding to the Cloud” Workshop at ICPE 2025. Declined due to travel constraints.
- Poster presentation, SC24 ACM Student Research Competition, Atlanta, GA, 2024.
- Poster presentation, UCI GEECS Showcase, Irvine, CA, 2024.
- Poster presentation, Young Fellow Program, 60th Design Automation Conference, San Francisco, CA, 2023.
- Presentation, LATTE ‘23, Workshop on Languages, Tools, and Techniques for Accelerator Design, 2023. “PyAIE: A Python-based Compiler Framework for Versal ACAP Platforms.”
Education
- University of California, Irvine, Ph.D. in Computer Engineering, 2022 – 2027 expected.
- University of California, Irvine, M.S. in Electrical and Computer Engineering, 2020 – 2022.
- University of California, Riverside, Graduate Preparation Program in Engineering (one-year exchange), 2019 – 2020.
- University of British Columbia, Vancouver Summer Program in Communication Systems and Digital Systems Design with FPGA, 2018.
- Northwestern Polytechnical University, B.Eng. in Microelectronics Science and Engineering, 2016 – 2020.