Hongzheng Tian
Ph.D. Candidate in Computer Engineering, University of California, Irvine
EECS, UC Irvine
CORSA Research Group
hongzhet [at] uci [dot] edu
I am a Ph.D. candidate in Computer Engineering at the EECS Department of the University of California, Irvine, advised by Prof. Sitao Huang in the CORSA research group. I expect to graduate in June 2027.
My research focuses on compilers and runtime systems for heterogeneous computing. My thesis project, CoVA (Compiler for Versatile Architectures), is an MLIR-based compiler that maps NumPy programs to CPUs and GPUs. Related projects include HeteroTask, a distributed task runtime with offline DAG scheduling for CPU/GPU nodes, and HeteroBench, a CPU/GPU/FPGA benchmark suite that received the ICPE 2025 Best Paper Award - Artifact Track.
I am broadly interested in compiler infrastructure for heterogeneous systems, performance portability, accelerator design automation, and practical tools that help researchers and developers reason about efficiency across modern hardware.
I am on the job market and looking for full-time roles in compilers and heterogeneous computing starting in 2027.
news
| Oct 12, 2026 | I am on the job market for full-time roles in compilers and heterogeneous computing, graduating in June 2027. |
|---|---|
| Sep 19, 2025 | Co-authored journal paper “A Sparsity-Aware Autonomous Path Planning Accelerator with HW/SW Co-Design and Multi-Level Dataflow Optimization” was published in ACM TACO. |
| Jun 04, 2025 | Advanced to Ph.D. candidacy in Computer Engineering at UC Irvine. |
| May 05, 2025 | HeteroBench was presented at ICPE 2025 and received the Best Paper Award - Artifact Track. |
| Nov 17, 2024 | Presented CoVA at the SC24 ACM Student Research Competition. |
| Oct 27, 2024 | Co-authored paper “A Sparsity-Aware Autonomous Path Planning Accelerator with Algorithm-Architecture Co-Design” appeared at ICCAD 2024. |
| Oct 09, 2024 | Co-authored preprint “Optimized Spatial Architecture Mapping Flow for Transformer Accelerators” released on arXiv. |
| Jul 09, 2023 | Presented PyAIE as a Late Breaking Result at the 60th Design Automation Conference (DAC 2023) in San Francisco and took part in the DAC Young Fellow program. |
| Mar 26, 2023 | Presented PyAIE, a Python-based compiler framework for AMD Versal ACAP, at LATTE ‘23, co-located with ASPLOS 2023 in Vancouver. |
| Mar 24, 2023 | My first-author paper “FPGA Implementation of Associative Processors” was published in IEEE Transactions on Circuits and Systems II: Express Briefs; it was later presented at ISCAS 2023 in May. |